Product Summary

The CY7C0852V133BBC is a kind of FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM. The FLEx36 family includes 1M, 2M, 4M and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided in CY7C0852V133BBC, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

Parametrics

CY7C0852V133BBC absolute maximum ratings: (1)Storage Temperature: –65℃ to + 150℃; (2)Ambient Temperature with Power Applied: –55℃ to + 125℃; (3)Supply Voltage to Ground Potential: –0.5V to + 4.6V; (4)DC Voltage Applied to Outputs in High-Z State: –0.5V to VDD + 0.5V; (5)DC Input Voltage: –0.5V to VDD + 0.5V; (6)Output Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage (JEDEC JESD22-A114-2000B): > 2000V; (8)Latch-up Current: > 200 mA.

Features

CY7C0852V133BBC features: (1)True dual-ported memory cells that allow simultaneous access of the same memory location; (2)Synchronous pipelined operation; (3)Organization of 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit devices; (4)Pipelined output mode allows fast operation; (5)0.18-micron CMOS for optimum speed and power; (6)High-speed clock to data access; (7)3.3V low power; (8)Global master reset; (9)Separate byte enables on both ports; (10)Commercial and industrial temperature ranges; (11)IEEE 1149.1-compatible JTAG boundary scan; (12)172-ball FBGA (1 mm pitch) (15 mm 15 mm); (13)176-pin TQFP (24 mmx24 mmx1.4 mm); (14)Counter wrap around control; (15)Counter readback on address lines; (16)Mask register readback on address lines; (17)Dual Chip Enables on both ports for easy depth expansion.

Diagrams

CY7C0852V133BBC circuit diagram

CY7C006
CY7C006

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Data Sheet

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CY7C006A

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Data Sheet

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CY7C006A-15AXC

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Data Sheet

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Data Sheet

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CY7C006A-20AXC

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Data Sheet

0-1: $16.80
1-25: $13.44
25-100: $12.59
100-250: $11.76