(Hong Kong)
Product Summary
The PA7140J20 is a Programmable Electrically Erasable Logic Array. It is based on ICT’s CMOS EEPROM technology. PEEL Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7140J20 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells. Each group shares half (60) of the 120 product-terms available for logic cells.
Parametrics
PA7140J20 absolute maximum ratings: (1)VCC, Supply Voltage Relative to Ground: -0.5 to + 7.0 V; (2)VI, VO, Voltage Applied to Any Pin Relative to Ground: -0.5 to VCC + 0.6 V; (3)IO, Output Current Per pin (IOL, IOH): ±25mA; (4)TST, Storage Temperature: -65 to + 150℃; (5)TLT, Lead Temperature Soldering 10 seconds: +300℃.
Features
PA7140J20 features: (1)24 I/Os, 14 inputs, 60 registers/latches; (2)Up to 72 logic cell output functions; (3)PLA structure with true product-term sharing; (4)Logic functions and registers can be I/O-buried; (5)Up to 3 output functions per logic cell; (6)D,T and JK registers with special features; (7)Independent or global clocks, resets, presets, clock polarity and output enables ; (8)Sum-of-products logic for output enables.
Diagrams
